Controlled Impedance Design

Controlled impedance keeps high-speed signals — DDR, PCIe, USB, Ethernet, LVDS — reflection-free by holding trace geometry and dielectric to a defined characteristic impedance. We build the stackup with a 2D field solver, not rule-of-thumb tables.

Field-solver stackups

We model each signal layer against its reference planes, accounting for:

• Dielectric constant (Dk) and loss (Df) at the operating frequency, per the actual laminate datasheet.
• Copper weight and etch-back trapezoid, which shifts real impedance from the drawn width.
• Solder mask and prepreg resin content, which alter the effective Dk near the surface.

Single-ended and differential

We tune line width, spacing, and layer height to hit target within ±5%, and account for coupling in tightly routed differential pairs.

Verification coupons

Every controlled-impedance job carries a TDR impedance coupon on the panel, built from the same materials on the same layers. The fabricator measures it with a time-domain reflectometer and reports actual impedance, giving you traceable proof rather than a modeled assumption.

The deliverable is a solver-backed stackup drawing, per-layer trace-width tables, and coupon definitions ready for CAM panelization.