HDI & Microvia Engineering

High-Density Interconnect is what makes modern fine-pitch BGAs, CSPs, and SoCs routable. We engineer HDI stackups and via architectures that hit density targets while staying inside the fabricator's lamination and plating window.

Microvia architecture

Microvias are laser-drilled, typically 0.075-0.15 mm, connecting adjacent layers. We design:

• Staggered microvias — offset between layers for maximum reliability.
• Stacked microvias — vertically aligned and copper-filled for the tightest escape, at higher process cost.
• Skip vias — spanning two dielectric layers where the fab qualifies it.

Sequential lamination

HDI is built in stages. An N build-up (e.g. 2-N-2, 3-N-3) laminates and drills sub-cores in sequence around a laminated core. Each cycle adds cost and thermal history, so we minimize build-up count while meeting the breakout demand.

Via-in-pad

Via-in-pad is mandatory below roughly 0.5 mm BGA pitch. We specify copper-filled and planarized microvias to prevent solder wicking and void formation, and coordinate the fill/cap process with the fab.

Aspect ratio governs plating throw and reliability. We keep microvia aspect ratios conservative and validate every buried-via plating path, then hand off to controlled-impedance tuning where signal integrity is in play.